\doxysection{LL\+\_\+\+UTILS\+\_\+\+Clk\+Init\+Type\+Def Struct Reference}
\hypertarget{struct_l_l___u_t_i_l_s___clk_init_type_def}{}\label{struct_l_l___u_t_i_l_s___clk_init_type_def}\index{LL\_UTILS\_ClkInitTypeDef@{LL\_UTILS\_ClkInitTypeDef}}


UTILS System, AHB and APB buses clock configuration structure definition.  




{\ttfamily \#include $<$stm32h7xx\+\_\+ll\+\_\+utils.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_l_l___u_t_i_l_s___clk_init_type_def_a13f6fcf896f6a10c5333125de2cb399d}{SYSCLKDivider}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_l_l___u_t_i_l_s___clk_init_type_def_a8674805c27fb68e07cdc60a9debe5d5e}{AHBCLKDivider}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_l_l___u_t_i_l_s___clk_init_type_def_a145153593da600e7840fb1351c95d0d5}{APB1\+CLKDivider}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_l_l___u_t_i_l_s___clk_init_type_def_a4e41c3fb594226ee0d7b8a0566b51530}{APB2\+CLKDivider}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_l_l___u_t_i_l_s___clk_init_type_def_accda0dc30ff5c4f85ccfe6df92a6938e}{APB3\+CLKDivider}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_l_l___u_t_i_l_s___clk_init_type_def_a6b6cf28a2eab995894ca8bde7a348dfb}{APB4\+CLKDivider}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
UTILS System, AHB and APB buses clock configuration structure definition. 

\label{doc-variable-members}
\Hypertarget{struct_l_l___u_t_i_l_s___clk_init_type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_l_l___u_t_i_l_s___clk_init_type_def_a8674805c27fb68e07cdc60a9debe5d5e}\index{LL\_UTILS\_ClkInitTypeDef@{LL\_UTILS\_ClkInitTypeDef}!AHBCLKDivider@{AHBCLKDivider}}
\index{AHBCLKDivider@{AHBCLKDivider}!LL\_UTILS\_ClkInitTypeDef@{LL\_UTILS\_ClkInitTypeDef}}
\doxysubsubsection{\texorpdfstring{AHBCLKDivider}{AHBCLKDivider}}
{\footnotesize\ttfamily \label{struct_l_l___u_t_i_l_s___clk_init_type_def_a8674805c27fb68e07cdc60a9debe5d5e} 
uint32\+\_\+t LL\+\_\+\+UTILS\+\_\+\+Clk\+Init\+Type\+Def\+::\+AHBCLKDivider}

The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of RCC\+\_\+\+LL\+\_\+\+EC\+\_\+\+AHB\+\_\+\+DIV

This feature can be modified afterwards using unitary function LL\+\_\+\+RCC\+\_\+\+Set\+AHBPrescaler(). \Hypertarget{struct_l_l___u_t_i_l_s___clk_init_type_def_a145153593da600e7840fb1351c95d0d5}\index{LL\_UTILS\_ClkInitTypeDef@{LL\_UTILS\_ClkInitTypeDef}!APB1CLKDivider@{APB1CLKDivider}}
\index{APB1CLKDivider@{APB1CLKDivider}!LL\_UTILS\_ClkInitTypeDef@{LL\_UTILS\_ClkInitTypeDef}}
\doxysubsubsection{\texorpdfstring{APB1CLKDivider}{APB1CLKDivider}}
{\footnotesize\ttfamily \label{struct_l_l___u_t_i_l_s___clk_init_type_def_a145153593da600e7840fb1351c95d0d5} 
uint32\+\_\+t LL\+\_\+\+UTILS\+\_\+\+Clk\+Init\+Type\+Def\+::\+APB1\+CLKDivider}

The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of RCC\+\_\+\+LL\+\_\+\+EC\+\_\+\+APB1\+\_\+\+DIV

This feature can be modified afterwards using unitary function LL\+\_\+\+RCC\+\_\+\+Set\+APB1\+Prescaler(). \Hypertarget{struct_l_l___u_t_i_l_s___clk_init_type_def_a4e41c3fb594226ee0d7b8a0566b51530}\index{LL\_UTILS\_ClkInitTypeDef@{LL\_UTILS\_ClkInitTypeDef}!APB2CLKDivider@{APB2CLKDivider}}
\index{APB2CLKDivider@{APB2CLKDivider}!LL\_UTILS\_ClkInitTypeDef@{LL\_UTILS\_ClkInitTypeDef}}
\doxysubsubsection{\texorpdfstring{APB2CLKDivider}{APB2CLKDivider}}
{\footnotesize\ttfamily \label{struct_l_l___u_t_i_l_s___clk_init_type_def_a4e41c3fb594226ee0d7b8a0566b51530} 
uint32\+\_\+t LL\+\_\+\+UTILS\+\_\+\+Clk\+Init\+Type\+Def\+::\+APB2\+CLKDivider}

The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of RCC\+\_\+\+LL\+\_\+\+EC\+\_\+\+APB2\+\_\+\+DIV

This feature can be modified afterwards using unitary function LL\+\_\+\+RCC\+\_\+\+Set\+APB2\+Prescaler(). \Hypertarget{struct_l_l___u_t_i_l_s___clk_init_type_def_accda0dc30ff5c4f85ccfe6df92a6938e}\index{LL\_UTILS\_ClkInitTypeDef@{LL\_UTILS\_ClkInitTypeDef}!APB3CLKDivider@{APB3CLKDivider}}
\index{APB3CLKDivider@{APB3CLKDivider}!LL\_UTILS\_ClkInitTypeDef@{LL\_UTILS\_ClkInitTypeDef}}
\doxysubsubsection{\texorpdfstring{APB3CLKDivider}{APB3CLKDivider}}
{\footnotesize\ttfamily \label{struct_l_l___u_t_i_l_s___clk_init_type_def_accda0dc30ff5c4f85ccfe6df92a6938e} 
uint32\+\_\+t LL\+\_\+\+UTILS\+\_\+\+Clk\+Init\+Type\+Def\+::\+APB3\+CLKDivider}

The APB2 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of RCC\+\_\+\+LL\+\_\+\+EC\+\_\+\+APB3\+\_\+\+DIV

This feature can be modified afterwards using unitary function LL\+\_\+\+RCC\+\_\+\+Set\+APB3\+Prescaler(). \Hypertarget{struct_l_l___u_t_i_l_s___clk_init_type_def_a6b6cf28a2eab995894ca8bde7a348dfb}\index{LL\_UTILS\_ClkInitTypeDef@{LL\_UTILS\_ClkInitTypeDef}!APB4CLKDivider@{APB4CLKDivider}}
\index{APB4CLKDivider@{APB4CLKDivider}!LL\_UTILS\_ClkInitTypeDef@{LL\_UTILS\_ClkInitTypeDef}}
\doxysubsubsection{\texorpdfstring{APB4CLKDivider}{APB4CLKDivider}}
{\footnotesize\ttfamily \label{struct_l_l___u_t_i_l_s___clk_init_type_def_a6b6cf28a2eab995894ca8bde7a348dfb} 
uint32\+\_\+t LL\+\_\+\+UTILS\+\_\+\+Clk\+Init\+Type\+Def\+::\+APB4\+CLKDivider}

The APB4 clock (PCLK4) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of RCC\+\_\+\+LL\+\_\+\+EC\+\_\+\+APB4\+\_\+\+DIV

This feature can be modified afterwards using unitary function LL\+\_\+\+RCC\+\_\+\+Set\+APB4\+Prescaler(). \Hypertarget{struct_l_l___u_t_i_l_s___clk_init_type_def_a13f6fcf896f6a10c5333125de2cb399d}\index{LL\_UTILS\_ClkInitTypeDef@{LL\_UTILS\_ClkInitTypeDef}!SYSCLKDivider@{SYSCLKDivider}}
\index{SYSCLKDivider@{SYSCLKDivider}!LL\_UTILS\_ClkInitTypeDef@{LL\_UTILS\_ClkInitTypeDef}}
\doxysubsubsection{\texorpdfstring{SYSCLKDivider}{SYSCLKDivider}}
{\footnotesize\ttfamily \label{struct_l_l___u_t_i_l_s___clk_init_type_def_a13f6fcf896f6a10c5333125de2cb399d} 
uint32\+\_\+t LL\+\_\+\+UTILS\+\_\+\+Clk\+Init\+Type\+Def\+::\+SYSCLKDivider}

The System clock (SYSCLK) divider. This clock is derived from the PLL output. This parameter can be a value of RCC\+\_\+\+LL\+\_\+\+EC\+\_\+\+SYSCLK\+\_\+\+DIV

This feature can be modified afterwards using unitary function LL\+\_\+\+RCC\+\_\+\+Set\+Sys\+Prescaler(). 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+STM32\+H7xx\+\_\+\+HAL\+\_\+\+Driver/\+Inc/\mbox{\hyperlink{stm32h7xx__ll__utils_8h}{stm32h7xx\+\_\+ll\+\_\+utils.\+h}}\end{DoxyCompactItemize}
